TC-7 Code to Write

Tip

Information on MIPS R2000 assembly instructions may be found in SPIM manual.

The MIPS Architecture Instruction Set is also a recommended reading.

You can run the MIPS using Nolimips.

Relevant pages:

For the The src/target/mips Directory folder you will find more information on this part in the book (Modern Compiler Implementation), in the chapter “9. Instruction Selection”.

src/target/mips/spim-matcher.cc

target::mips::SpimMatcher is the functor used for instruction selection pattern-matching.

src/target/mips/spim-assembly.cc

SpimAssembly::move_build builds a move instruction using MIPS R2000 standard instruction set.
SpimAssembly::binop_inst, SpimAssembly::binop_build build arithmetic binary operations (addition, multiplication, etc.) using MIPS R2000 standard instruction set.
SpimAssembly::load_build, SpimAssembly::store_build build a load (respectively a store) instruction using MIPS R2000 standard instruction set. Here, the indirect addressing mode is used.
SpimAssembly::cjump_build translates conditional branch instructions (branch if equal, if lower than, etc.) into MIPS R2000 assembly.

Runtime

You have to complete the implementation of the runtime in src/target/mips/runtime.s:

strcmp
streq
print_int
substring
concat

Warning

Strings are implemented as 4 bytes to encode the length, and then a 0-terminated C-like string. You should rely on the initial encoded length, which is always present for compliance.

See the example below on how the string data is represented (l0):

hello-world.tig

print("Hello Tiger!")

tc --nolimips-display hello-world.tig | head -n 5

$ tc --nolimips-display hello-world.tig | head -n 5
# == Final assembler ouput. == #
.data
l0:
	.word 12
	.asciiz "Hello Tiger!"
$ echo $?
0

String data representation (assuming little endian)
Address (`l0` +)	0x00	0x01	0x02	0x03	0x04	0x05	…	0x10
Value	0x00	0x00	0x00	0x0c	`'H'`	`'e'`	…	`'\0'`

src/target/mips/spim-codegen.cc (Optional): Completing the Codegen::rewrite_program routine will be needed during register allocation only, see TC-9, Register Allocation.